The BioSCAN ASIC was designed using 1.2-micron scalable CMOS design rules from MOSIS and fabricated by Hewlett-Packard. Each 7.75 mm x 9 mm die contains 812 PEs. Sixty-five of the 108 devices tested with zero defects. Eight other devices had a few defective PEs that can be programmed out from the array. Thus, the overall processing yield of usable devices was 67%. A summary of design and process parameters for the chip is given below. BioSCAN ASIC Device Summary Die Size Transistors Processors Pins/Package Clock Voltage/Power Interface Process Gate length/tox Poly/Metal1/Metal2 7750 micron x 9050 micron 537,675 (89,736 in RAM) 812 (536 transistors/PE) 84 pin PGA (42 Vdd/GND) 32 MHz @ 50 deg-C (ambient) 4.75-5.25V (3.0W max) TTL-compatible 1.2 micron N-well CMOS 1.2 micron / 20 nm 2.4/3.6/4.2 micron pitch