Table of contentsChapter 8: Main Memory Chapter 8: Memory Management Objectives Background Base and Limit Registers Binding of Instructions and Data to Memory Multistep Processing of a User Program Logical vs. Physical Address Space Memory-Management Unit (MMU) Dynamic relocation using a relocation register Dynamic Loading Dynamic Linking Swapping Schematic View of Swapping Contiguous Allocation HW address protection with base and limit registers Contiguous Allocation (Cont.) Dynamic Storage-Allocation Problem Fragmentation Paging Address Translation Scheme Paging Hardware Paging Model of Logical and Physical Memory Paging Example Free Frames Implementation of Page Table Associative Memory Paging Hardware With TLB Effective Access Time Memory Protection Valid (v) or Invalid (i) Bit In A Page Table Shared Pages Shared Pages Example Structure of the Page Table Hierarchical Page Tables Two-Level Page-Table Scheme Two-Level Paging Example Address-Translation Scheme Three-level Paging Scheme Hashed Page Tables Hashed Page Table Inverted Page Table Inverted Page Table Architecture Segmentation User’s View of a Program Logical View of Segmentation Segmentation Architecture Segmentation Architecture (Cont.) Segmentation Hardware Example of Segmentation Example: The Intel Pentium Logical to Physical Address Translation in Pentium Intel Pentium Segmentation Pentium Paging Architecture Linear Address in Linux Three-level Paging in Linux End of Chapter 8 |
Author: Silberschatz, galvin, and Gagne Homepage: http://www.cs.yale.edu/homes/avi/os-book/os7/index.html Further information: |