CSCI 330 Instruction Level Parallelism Part 2

Review from Last Time #1

Review from Last Time #2

Outline

Instruction Level Parallelism Part 2

Speculation to greater ILP

Slide 7

Adding Speculation to Tomasulo

Reorder Buffer (ROB)

Reorder Buffer Entry

Reorder Buffer operation

Recall: 4 Steps of Speculative Tomasulo Algorithm

Avoiding Memory Hazards

Exceptions and Interrupts

VLIW

Getting CPI below 1

VLIW: Very Large Instruction Word

Recall: Unrolled Loop that Minimizes Stalls for Scalar

Loop Unrolling in VLIW

Problems with 1st Generation VLIW

Intel/HP IA-64 “Explicitly Parallel Instruction Computer (EPIC)”

Increasing Instruction Fetch Bandwidth

IF BW: Return Address Predictor

More Instruction Fetch Bandwidth

Speculation: Register Renaming vs. ROB

Value Prediction

Perspective

Summary

In Conclusion …

Next Time…